Abstract Fault diagnosis with a dimension reduction based on Bayesian approach is proposed in this paper. The first step is to generate a sample (parameter) of fault-free mode class and faulty mode class. The second, in order to obtain good classification performance, a selection of important features is done with the discrete karhunen-loeve expansion. Next, the Bayes test for minimum error is used to classify the classes. Finally, the results for simulated data demonstrate the capabilities of the proposed procedure.
, , , , (11-2015)

Line commutated current source converter based HVDC (LCC HVDC) systems are being applied to transfer power from remote wind resources to interconnect to existing ac transmission systems. The rectifier terminals of these systems are connected to weak ac systems. HVDC system design engineers have extensive experience implementing dynamic reactive compensation solutions when the inverter end of the system is weak, but the guidelines used overstate the reactive compensation needed for rectifier operation. A modified CIGRE HVDC benchmark model in PSCAD/EMTDC program is used to perform this study the impact of varying amounts of dynamic reactive compensation for rectifier operation. Simulation results will also compare the effectiveness of synchronous condensers versus static synchronous compensators (STATCOMs) in reducing incidents of commutation failures at the rectifier bus of the LCC HVDC transmission system
د. براين جونسون, د. هيس هرب, , (12-2014)

The end to end transfer of data from a transmitting application to receiving application involves many steps, each subject to error, with adequate error control, we can be confident that the transmitted and received data are identical , errors can occur at both the bits and packet levels. error control is the process of detecting and correcting both bit and packet errors. In this paper we show combination codes of error control schemes using forward error correction, which keeping an efficient use of the limited bandwidth. we use a Hamming (7,4) code and (12,8) code, in which three checks bits are combined with four information bits to produce a block of data of length n=7 for (7,4) code, and which four checks bits are combined with eight information bits to produce a block of data of length n=12 for (12,8) code. A block of data of length 12 is to short to be appropriate for practical data communications system, but the mathematics involved in longer blocks would become tedious.
سليمان خليفة على يخلف, (6-2013)